1. Field of the Invention
This invention relates to a semiconductor memory device, a power supply detector and a semiconductor device each having a circuit for detecting an applying of an external power supply.
2. Description of the Related Art
Recently, with the widespread use of mobile instruments such as the portable telephone, it has been required to provide low power, low voltage operation and reliability at a wide temperature range. Under the circumstances, various problems which have not been considered conventionally have appeared. As one of the problems, there is an operation margin of a power supply input detection circuit (power-on circuit). The power input detecting circuit is for outputting a trigger signal to apply a voltage used in a semiconductor memory device by detecting that power from the outside is supplied.
In the semiconductor memory device used in mobile equipment and the like, MOSFETs (Metal-Oxide-Semiconductor Field Effect Transistor) which have a relatively high threshold (Vth) are adopted due to low power usage, wherein it is required to have a safety margin for low voltage operation and operational guarantee at a wide temperature range (for example, −40 to 100 degrees Celsius). Accordingly, it is required to have sufficient margins in the power supply input detection circuit of the power system.
In connection with these requirements, in a typical power supply input detection circuit using a diode-connected p-channel type MOSFET, the effect by the temperature dependant properties of a threshold of the p-channel type MOSFET is significant. Therefore, it is difficult to secure sufficient margin with respect to both a minimum power voltage value which can correctly latch a fuse data (fuse-latch limit voltage) and minimum power voltage value at which the semiconductor memory device can operate. That is, in a typical power supply input detection circuit, as the requirements of lower power, low voltage operation and wide temperature range operability become severe, since operational margins becomes insufficient, it is expected that the semiconductor memory device could not exhibit adequate performance.
As a known technique relating to the power supply input detection circuit, the use of a diode-connected n-channel MOS transistor having a gate and a drain connected (see, for example, Japanese Patent Laid-open Application Hei 9-181586, FIG. 2 and paragraph 0018). However, as described therein, when the structure in which the gate and the drain of the n-channel MOS transistor are connected is adopted, it is difficult to suitably perform the detection of power-on at a low power voltage and low temperature, because a threshold increases due to the back-bias effect.